QEMU user mode support for the new Cortex-A15 instructions

draft r0

The Cortex-A15 is the first Cortex-A processor to include the VFPv4 floating point unit and integer divide instructions. This project implemented these new instructions in QEMU so that QEMU user mode could be used to run Cortex-A15 programs such as the GCC test suite and tools like linaro-media-tools.


Where to find it

The new instructions are:

  • The VFPv4 fused multiply-accumulate (FMA) family
  • The core signed and unsigned divide instructions

Support is available in both http://qemu.org/ trunk from November, 2011 and is included in the QEMU 1.0 release Linaro QEMU 2011.11 release.


GCC trunk and Linaro GCC 4.6 2012.01 include support for the Cortex-A15 and will emit divide instructions. There is currently no support for FMA.


The following instructions were implemented or enabled:

  • Fused multiply-add: VFMA, VFMS, VFNMA, VFNMS
  • Divide: UDIV, SDIV in Thumb2 and ARM modes.

Testing was performed on an x86 host running cross-compiled or generated programs against a user mode guest.

The instructions were tested using the Risu random-instruction-sequence tester against a FPGA based Cortex-A15. The following instruction patterns were used:

VFM A1 1111 0010 0 d op sz vn:4 vd:4 1100 n q m 1 vm:4
VFM A2 cond:4 11101 d 10 vn:4 vd:4 101 sz n op m 0 vm:4
VFNM A1 cond:4 11101 d 01 vn:4 vd:4 101 sz n op m 0 vm:4
SDIV A1 cond:4 01110 001 rd:4 1111 rm:4 000 1 rn:4
UDIV A1 cond:4 01110 011 rd:4 1111 rm:4 000 1 rn:4
SDIV T1 11111 011100 1 rn:4 1111 rd:4 1111 rm:4
UDIV T1 11111 011101 1 rn:4 1111 rd:4 1111 rm:4

Risu generates runs of random instructions which match the specified patterns. The registers are initialised with biased random values, and every 100 generated instructions they are re-initialised with more random data. The biasing of the data is intended to increase the chances of testing "interesting" floating point values, and is as follows:

  • float +0 : 1.25%
  • float -0 : 1.25%
  • float NaN : 2.5%
  • float +Inf : 1.25%
  • float -Inf : 1.25%
  • float denormal : 7.5%
  • float normal : 35%
  • double +0 : 1.25%
  • double -0 : 1.25%
  • double NaN : 2.5%
  • double +Inf : 1.25%
  • double -Inf : 1.25%
  • double denormal : 7.5%
  • double normal : 35%

After every randomly generated instruction the resulting register values are compared against a 'known good' host. This includes the IEEE exception flags from the FPSCR. Runs were done for all the FPSCR-controlled rounding mode settings (100,000 instructions each). A run of at least 1,000,000 random instructions was done for the default rounding mode to ensure coverage.

Future Work

No future work is planned in this area. A related area is the Cortex-A15 system model work planned as part of KVM.

The blueprint is here:

The work was done by:

Work was completed in November 2011.

WorkingGroups/ToolChain/Outputs/A15UserMode (last modified 2012-01-23 23:01:43)