Monday 12th December 2011
This month's meetings
<< < 2011 / 12 > >>
- Review action items from last meeting
- Release week follow up
- What needs to be documented
- Alignment on vectorised loads and stores
- cdce3.C execution test failure
- gcc-4.6+svn179644, gcc-4.6+svn179959, gcc-4.6+svn180286, gcc-4.6+svn180601
- gcc-4.6+svn180925, gcc-4.6+svn181280, gcc-4.6+svn181466, gcc-4.6+svn181709
- gcc-4.6+svn181902, gcc-4.6+svn182154
- OpenOCD investigation
- The 4.6 release branch
- O3 progress
- Outline of the writeup
Action Items from this Meeting
Action Items from Previous Meeting
- INPROGRESS: Andrew to try Julian again on 675347
- DONE: Ramana to backport A15 and VCVT patches from upstream.
- DONE: Andrew to spin GCC releases on Tuesday.
- DONE: Dave to merge 64 bit operations for this month's release
Release week follow up:
- What needs documentation/polish?
- ubutest and benchmarking
- Couldn't find the logs!
- Couldn't find the benchmarking results for anything but ARM
- glibc and python tests failed
- Did not complete building the package
- Dependency on a newer libgcc?
- So why did the 4.5 one fail?
- During the shlibs deps stage
- Had trouble with the key signing, Ulrich helped
- Tidy up perhaps?
- Needs documentation
- ACTION: Andrew to update release notes to match
- Is there an easy way to disable biarch?
- ACTION: Michael to patch to disable biarch
- Ramana isn't happy doing it by himself
- Run again after removing the wrinkles
- Liked the idea of sending the release notes out early
- Start doing as a wiki page
- Perhaps have a release note entry with every interesting checkin
Or an extra line in the ChangeLog?
- ...which is partly due to RCS in the dim distant past
Alignment on vectorised loads and stores:
- Ramana has been having a look at it
- Bug in test case with 128 bit alignment
- Working on backend to generate the vld1 instructions
- Why was it generating vldmia?
- Memory model/ABI requires that you use something equivalent to vldm
- ...which is vld1 in little endian
- as external vector format is *always* lowest vector lane goes into lane 0 when parameter passing
- which is different in big endian GCC
- Don't expect to regress A8 performance
- Dave has seen cases where a [r0:256] gives him a cycle back
- ACTION: Michael to spin a template blueprint
cdce3.C execution test failure:
- Has been seen many times
- Can repeat
- Need to repeat locally, grab the executable
- See if the problem goes away with a sequential build
- Building minimal image - kernel and shell and not much more
- Builds with the CSL binary compiler
- Once we hit a certain number of packages, switch to Linaro
- Switch to a A9 Thumb-2 NEON configuration
- Outline of the writeup
- Performance regressions
- Do we know enough about the regressions at -O3?
- Want to at least understand all the significant regressions
- Was Connect better? Can we reproduce that
- For next time want .i files, perf, and similar
- With those it might be as good remotely
- Doing perf
- Perhaps do by hand
- Perhaps do automatically in the future?
- Partial PRE
- Back/cross porting from the PR
- Has to do on trunk as well
- FSF has complained
- Debian needs these...
- Fedora needs these...
- ACTION: Michael and Richard to send an email to the other ARM branches proposing something
WorkingGroups/ToolChain/Meetings/Archive/2011-12-12 (last modified 2013-08-30 11:47:50)