- Spent the whole week attending Linaro@UDS. Any other activity this week is squeezed into the space between (interesting) sessions.
Finished making the suggested changes to my Thumb2 constants patch, and posted it back upstream. This is pre-approved, but can't be committed until after the addw/subw patch. http://firstname.lastname@example.org/msg05195.html
- Merged all my outstanding approved merge requests to the release branches in time for next week's release.
- At Linaro@UDS; I am still typing this in Budapest. Sparingly did some work between sessions.
- PR42017, ARM LR register not being used. Discussed the patch with Richard Sandiford at LDS. Re-tested a bit and about to resend a revised patch according to his suggestion.
748138, redirect_jump() ICE. Committed patch to CS stable and trunk. Submitted merge request to Linaro 4.5 branch.
689887. Got some suggestions from Revital on how to debug the bootstrap failure caused by my patch, will look into applying it.
- Taking Monday off, I'll be flying back to Taiwan on Tuesday.
- Continue with issues after getting home.
- Gave up on perf on silverbell and redid it on ursa2; now have a full set of perf figures and have updated the workload report to show the spec binaries that use significant time in libc and the routines they spend it in; a handful of tests spend very significant amounts of time in libm.
- Have ltrace results from about 75% of spec - some of the others are fighting a bit
Optimised the non-neon memcpy; it's now quite respectable except in one or two cases (2 byte misaligned, and for some odd reason source offset by 8 bytes, destination by 12 is way down on any other combination) (Current result graphs here https://wiki.linaro.org/Internal/People/DaveGilbert?action=AttachFile&do=get&target=results-2011-05-13-panda-69321a21.pdf )
- continued looking into ffmpeg/libavcodec:
- dcadsp.c - the inner loop contains reverse accesses which are not supported on Neon. I think we can handle them using vrev and vswp.
- a lot of loops have unknown memory stride. I am exploring a possibility of a combination of scalar loads and vmov into a vector register, but it is probably too expensive.
- looking into telecom/conven
- Attended LDS from 9th -14th May.
- Look at Thumb2 performance blueprint and break it down.
- Investigate more headroom for SPEC2k starting this week.
- Thumb2 performance call this week.
- Attended Linaro@UDS.
- SMS patches to support ARM do-loop pattern got approved in mainline and merged into gcc-linaro 4.6 and 4.5.
- Sent merge request for two patches in trunk. (SMS_fixes_for_unfreed_memory)
- Implemented an optimization for the stage-count and now testing it.
WorkingGroups/ToolChain/ActivityReports/2011-05-13 (last modified 2011-05-17 13:37:46)